1. Technical Field
The present invention pertains to dynamic random access memories (DRAM). In particular, the present invention pertains to a refresh control unit for dynamic random access memories that controls the quantity of refresh cycles performed in a plural refresh cycle scheme for a refresh command.
2. Discussion of Related Art
Generally, a dynamic random access memory (DRAM) includes a plurality of memory cells each including one or more transistors and a data storage capacitor. The cells are typically arranged into one or more memory banks, with each bank in the form of a matrix of rows and columns. Since the respective charges of the cells are allowed to leak, the memory cells must be refreshed periodically to prevent data loss. A refresh operation typically selects one word line or row based on the content of a refresh address counter, where the memory cells connected to the selected word line are refreshed. The refresh operation may be initiated by an auto-refresh or automatically generated refresh command. This command may be generated internally (e.g., internal memory controller, etc.) or by an external source (e.g., controller, processor, etc.) and is associated with a particular quantity of memory rows or word lines to be refreshed.
A single cycle refresh scheme is generally employed where only one row or word line is refreshed (e.g., one refresh cycle occurs) in response to an auto-refresh command. However, some dynamic memory devices require a greater number of row addresses to be refreshed in response to an auto-refresh command than that accommodated by the corresponding command refresh cycle. In order to comply with refresh requirements, plural row addresses may be accessed with an auto-refresh command. The plural addresses may be accessed in a parallel or consecutive manner. With respect to consecutive access, one or more internal refresh commands are generated in response to the initial auto-refresh command in order to automatically perform successive refresh operations.
An example of a conventional dynamic memory device employing a two cycle refresh scheme is illustrated in FIG. 1. In particular, the dynamic memory device includes a state machine 10, a row control block 20, an internal refresh command generator 30, a refresh control circuit 32 and one or more memory banks 34 each with corresponding row and column decoders 36, 38. The state machine basically serves as an instruction decoder and receives an auto-refresh command. This command may be generated internally (e.g., by a test mode generator, memory controller, etc.) or received from an external source (e.g., processor utilizing the memory device, controller, etc.) The state machine is coupled to row control block 20 and internal refresh command generator 30 and provides a refresh signal (REFRESH) in an active or high logic level state to these devices in response to decoding an auto-refresh command. The row control block generates a row refresh signal (ROW_ACT_PCG) in an active or high logic level state that is provided to refresh circuit 32 to facilitate refreshing of a corresponding word line or row in one or more memory banks 34. Row decoder 36 accesses a row in the associated memory bank corresponding to a received address. The received address may be a refresh address for a refresh operation or an address of a desired memory location for a read and/or write operation. Column decoder 38 similarly accesses a column in the associated memory bank corresponding to a received address for the read and/or write operation. The refresh control circuit typically includes a refresh address counter 33 to provide the address of the corresponding word line or row to row decoders 36 of the appropriate memory banks in order to accomplish refresh of that row.
The internal refresh command generator produces an internal refresh command to initiate the second refresh cycle for the auto-refresh command to refresh an additional memory row or word line as described below. The above devices are typically implemented by conventional components (e.g., circuitry, decoders, state machines, logic, processors, etc.). For examples of conventional dynamic random access memory device configurations, reference is made to U.S. Pat. No. 6,373,769 (Kiehl et al), U.S. Pat. No. 6,603,694 (Frankowsky et al) and U.S. Pat. No. 6,614,704 (Dobler et al), the disclosures of which are incorporated herein by reference in their entireties.
The operation of the dynamic memory device is described with respect to the timing diagram illustrated in FIG. 2. Specifically, state machine 10 (FIG. 1) receives an external auto-refresh command (REF) and produces a positive pulse or activates a refresh signal (REFRESH) to commence an initial refresh cycle. The refresh signal is provided to row control block 20 and internal command generator 30. The active refresh signal enables the internal refresh command generator, and further enables the row control block to produce a row refresh signal (ROW_ACT_PCG) in an active or high logic level state. The active row refresh signal initiates the first refresh cycle and enables refresh control circuit 32 to refresh an associated memory row or word line. The word line is activated for a particular time interval or delay (tRAS) that is typically monitored by an internal timer. After the activation time interval (tRAS), the row refresh signal (ROW_ACT_PCG) enters a precharge or low logic level state automatically.
The row refresh signal (ROW_ACT_PCG) is further provided to internal refresh command generator 30, where the falling edge of the row refresh signal enables the internal command generator to produce a positive pulse or internal refresh signal (REF_INT) in an active or high logic level state. The internal refresh signal is generated automatically after another time interval or delay (tRP) to initiate a second refresh cycle. This time interval represents the delay needed between successive activations of word lines and is typically monitored by a second internal timer.
The row control block receives the active internal refresh signal (REF_INT) and activates the row refresh signal (ROW_ACT_PCG) to a high logic level state to initiate a refresh operation on a succeeding memory row or word line as described above. The internal refresh command generator is disabled in response to the active internal refresh signal since the auto-refresh command initiates a first refresh cycle and the internal refresh command initiates the second refresh cycle.
The row refresh signal (ROW_ACT_PCG) enters a precharge or low logic level state automatically after a time delay (tRAS) as described above. However, the falling edge of the row refresh signal does not facilitate activation of the internal refresh signal (REF_INT) since the internal command generator is disabled. Accordingly, the refresh operation is complete, where two refresh cycles are performed in response to an auto-refresh command. For an example of a plural cycle refresh scheme in a dynamic random access memory device, reference is made to U.S. Pat. No. 5,566,119 (Matano), the disclosure of which is incorporated herein by reference in its entirety.
The plural cycle refresh scheme described above has some difficulty in accommodating test methods employing single cycle refresh schemes since the successive row activations occur automatically. Generally, an auto-refresh command activates a greater number of word lines than an active row command. Thus, some test methods employ the auto-refresh command instead of an active row command for word line activation in order to achieve enhanced test efficiency. In order to use the auto-refresh command in the manner of a normal active row command, the active and precharged timing should be controlled externally. However, the auto-refresh command always enables the internal refresh command generator in the plural cycle refresh scheme described above, thereby precluding control of the successive row active timing. Thus, previously developed efficient test methods are generally not compatible with the plural cycle auto-refresh scheme or their use with such schemes is extremely complex.
The present invention provides a manner to control the quantity of refresh cycles in a plural cycle refresh scheme and may be utilized to alleviate the aforementioned problems.